Documentation

Installation

FPGAi is a Python CLI agent. Requires Python 3.10+ and pip.

pip install fpgai

For simulation features, also install iverilog (Icarus Verilog):

# macOS
brew install icarus-verilog

# Ubuntu / Debian
sudo apt install iverilog

# Windows (WSL recommended)
sudo apt install iverilog

Yosys (optional) enables synthesis checks after code generation. Install via your package manager or yosyshq.net.

Authentication

On first run (and after /logout), FPGAi shows a short setup wizard in the terminal. Your token is stored locally in ~/.fpgai/config.toml.

# First run launches the setup wizard automatically
fpgai

The wizard offers two ways to sign in:

To switch accounts later, run /logout inside FPGAi and restart it.

Basic Usage

Navigate to your Vivado project directory and start FPGAi. Type your request in natural language.

cd ~/vivado/my_project
fpgai

FPGAi writes files directly into your project directory. Every write is backed up automatically — use /undo to restore.

Slash Commands

Type these at the FPGAi prompt at any time. Press Tab to autocomplete commands and their arguments.

Self-Correcting Testbench

FPGAi's signature feature: it doesn't just generate a testbench — it runs it and fixes errors automatically.

Ask for a testbench in natural language (e.g. "write a testbench for uart_tx"), then run /simulate <file> to start the loop.

Self-correction requires iverilog on your PATH. Free plan users get basic testbench generation without self-correction; the Professional plan enables the full loop.

Synthesis Check

After writing a Verilog or SystemVerilog file, FPGAi automatically runs a synthesis check using Yosys (if installed).

Synthesis check is skipped if Yosys is not installed. Install it to catch latches, combinational loops, and unsynthesizable constructs before simulation.

Constraint Files

Generate XDC or SDC constraint files for popular FPGA boards.

# List supported boards
/constraints list

# Generate for a specific board
/constraints arty-a7-35t
/constraints basys3
/constraints de10-nano

Generated files include clock constraints and TODO markers for I/O pin assignments that require board-specific knowledge. See Supported Boards for the full list.

Project Context

FPGAi can read your existing project files and use them as context for generation and debugging.

You control this. Change the default in ~/.fpgai/config.toml under the code_sharing_mode key (query-only or full-context).

Model Selection

FPGAi supports multiple LLM backends. Your administrator configures available models; you can choose from what's enabled.

# Inside FPGAi, switch models with the /model command
/model

# Or set a default in ~/.fpgai/config.toml:
#   [preferences]
#   default_model = "claude-sonnet-4-6"

Hosted model usage is limited by your monthly AI usage credit plus prepaid credit. Team usage draws from the shared Team wallet first and then only the caller's personal wallet, so one member cannot spend another member's personal credit. Bring your own API key for any supported provider to pay provider token costs directly; chat, RAG, and PageIndex LLM calls use your key when BYOK is active.

Configuration

Config file lives at ~/.fpgai/config.toml. Edit it with any text editor.

[server]
url = "https://fpgaitool.com"

[preferences]
default_model = "claude-sonnet-4-6"
code_sharing_mode = "query-only"   # or "full-context"
auto_update_check = true

To point at a self-hosted instance, set the url under [server] in ~/.fpgai/config.toml.

Supported Boards

More boards coming soon. Request a board by opening a GitHub issue or contacting support.