AI FPGA Assistant.
Verilog, VHDL, Testbenches.
FPGAi generates self-correcting testbenches for your Verilog/VHDL modules. It proposes edge cases you didn't think of, runs simulation locally, and fixes errors automatically.
1-month free trial · no credit card required
Want to join the private beta? Start with a 1-month free trial. After the first month, beta access continues based on the feedback you share — active testers stay on for up to 3 months while their feedback keeps shaping the product.
Questions? Reach us at betatester@fpgaitool.com
FPGAi> Write an SPI master, 8-bit, CPOL=0, 100MHz Artix-7
model claude-sonnet-4 · mode full-context
✓ src/spi_master.v
✓ tb/spi_master_tb.v (11 scenarios)
✗ assertion failed @ t=1840ns — MISO sampled on wrong edge
→ patch applied: sample MISO on falling SCLK
✓ re-run: 11/11 tests passed
Use FPGAi directly inside VS Code
Chat with @fpgai, review HDL, attach diagrams, and apply generated files without leaving your editor.
Hosted chat and file apply work without the CLI. Local simulation, diagrams, waveforms, preflight lint, and diff workflows require the optional CLI agent.
Workflow
Three steps to verified HDL
From prompt to synthesizable, tested code — without leaving your terminal.
Install once
pip install fpgai — then authenticate with your FPGAi account. The agent lives on your machine.
Ask in plain English
Describe your module: interface, clock, reset strategy, FPGA family. FPGAi asks the right questions if anything is missing.
Ship verified code
Verilog + testbench are written to your project. Simulation runs locally. Errors are fixed automatically. Synthesis is checked.
Capabilities
Everything FPGA engineers need
Not a generalist AI. A specialist for digital design.
Self-Correcting Testbenches
AI generates testbenches, runs Icarus Verilog locally, and fixes errors automatically — up to 10 correction iterations, until all tests pass.
Synthesizable Code Generation
Describe what you need in natural language. Get timing-aware, synthesizable Verilog/VHDL that works on your target FPGA — Xilinx, Intel, Lattice, Gowin.
Synthesis Check
After writing RTL, automatically runs Yosys to check synthesizability, detect inferred latches, and report cell/wire counts — before you open Vivado.
FPGA-Specific RAG Knowledge
Searches Xilinx/Intel/Lattice documentation, AXI4/APB/Wishbone specs, and vendor guides before answering. Not a generalist — a specialist.
Constraint File Generation
Generate XDC or SDC constraint files for popular boards (Arty A7, Basys 3, DE10-Nano) with clock constraints and I/O TODO markers.
Debug & Timing Analysis
Paste your Vivado or Quartus error. Get the root cause and a targeted fix — not a generic answer, but one specific to your code and target device.
Works Inside Your Project
Lightweight CLI agent writes files directly into your project directory. Every write is backed up automatically. /undo restores instantly.
Switchable LLM Backends
Choose between Claude and DeepSeek V4 Pro. Use your own Anthropic or DeepSeek API key (BYOK), or let the platform handle it.
From beta sessions
Hours of work, minutes of waiting
Typical ranges shared by beta users — directional, not guarantees.
Private beta
Ready to put it on your next module?
We're onboarding FPGA engineers in small cohorts. Start the free trial and tell us where it helps — and where it doesn't.
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